The present invention relates to a semiconductor memory device and fabricating method thereof, and more particularly to a semiconductor memory device and fabricating method thereof having improved reliability and integration.
Recently, the packing density and performance of VLSI devices has been greatly advanced. In the field of MOS-type DRAMs, those of 16 Mb have begun to be produced in mass, with study now being focused on DRAMs having densities of 64 Mb and higher. In these higher-density DRAMs, since their cell size becomes minutely small (below approx. 1.5 .mu.m.sup.2), various three-dimensional capacitor structures or dielectrics having a high dielectric constant, such as a Ta.sub.2 O.sub.5 layer, have been considered.
Smaller cell size is made possible by reducing the distance between the conductor layers constituting a cell. Due to the higher integration, in DRAMs, the distance between gate electrodes set to a minimum feature size according to a design rule, becomes at least as small as the minimum feature size of a contact hole for connecting a bit line to a drain region or that connecting a storage electrode to a source region. This deteriorates device reliability.
FIG. 1 is a layout of a semiconductor memory device for illustrating a conventional fabricating method and a method of the present invention. In FIG. 1, a region defined by a dashed line outlining a zigzagged area is a mask pattern P1 for forming a field oxide layer for dividing a substrate into an active region and non-active region. Regions defined by solid lines into vertical rectangles throughout the substrate are mask patterns P2 for forming a gate electrode (word line). A region defined by a solid-lined square having diagonally crossing lines at the substrate's center is a mask pattern P3 for forming a contact hole for connecting a drain region of a transistor to a bit line. A region defined by a dash-and-dot line outlining a horizontal rectangle and containing mask pattern P3, is a mask pattern P4 for forming the bit line. A region within one end of mask pattern P1 and defined by a solid-lined square having one diagonally crossing line is a mask pattern P5 for connecting a storage electrode to a source region of the transistor.
FIG. 1 is a layout for forming a minimum-sized memory cell, which is formed to a minimum feature size according to its design rule. In FIG. 1, elliptical regions I, II and III indicate portions where conductor layers which should not be in contact with one another due to their different functions, do partly make contact with one another when the memory cell is fabricated based upon the layout. Here, region I indicates a portion in contact with the storage electrode and bit line, region II indicates a portion in contact with the storage electrode and gate electrode, and region Ill indicates a portion in contact with the bit line and gate electrode.
FIG. 2 is a cross-sectional view of a semiconductor memory device fabricated by a conventional method, taken along line AA' of FIG. 1.
In FIG. 2, circular portions A indicate contact portions with a bit line 30 and gate electrodes 18, illustrating region III of the layout. In order to minimize cell size, the distance between the gate electrodes is set to be equal to the width of a contact hole for bit line connection. However, in the memory device of FIG. 2 fabricated based upon the layout, the gate electrodes and bit line make contact with each other as in portion A because one side of the gate electrodes is exposed inside the contact hole due to an etching process for forming the contact hole. The contact problem between differently functioning conductor layers commonly takes place in regions I, II and III of FIG. 1, besides portion A. This is a main factor to paralyze normal operation. Circular portions B indicate portions having an excessively indented surface due to lower structures (transistor and bit line 30 in FIG. 2). The portions have a high possibility for creation of stringers during a process which deposits and etches a conductive material to form a storage electrode. Stringers contribute to the decrease of device reliability and are frequently created in portions having severely indented surfaces.
Since the semiconductor memory device fabricated by the above conventional method presents the problem of the creation of stringers in portions having severely indented surfaces or in contact with the conductor layers, the semiconductor device is unsuitable for memory devices having densities of 64 Mb and higher.